1. Field of the Invention
The present invention relates to semiconductor fabrication, and more particularly to a method for forming a transistor with strained channel.
2. Description of the Related Art
In modern semiconductor devices, bulk silicon is used as a substrate. Higher operating speed and lower energy consumption can be achieved by size reduction of the semiconductor devices formed thereon. Reduction of device size, however, is limited by device physics and fabrication costs. Thus, in addition to physical device size reduction, a different method is required to achieve the goals of higher operating speed and lower energy consumption.
For this reason, a method using stress control in the channel region of a transistor to overcome the limitation of size reduction is presented. The method increases mobility of electrons and holes using additional stress to vary silicon lattice spacing.
In conventional methods, a tensile-strained silicon layer disposed on a SiGe layer under tensile stresses acting as a channel layer of an NMOS transistor and a compressive-strained SiGe layer under compressive stresses acting as a channel layer of a PMOS transistor are disclosed. Through the silicon layer under tensile stresses and the SiGe layer under compressive stresses acting as the channel region of a MOS transistor, mobility of electrons and holes can be increased and higher operating speed and lower energy consumption can be achieved.
Nevertheless, some problems exist in the described methods, for example, the process for simultaneously forming a silicon substrate under tensile stresses (n-channel layer) and a SiGe layer under compressive stresses (p-channel layer) is complicated and methods of selectively forming an NMOS channel layer and a PMOS channel layer are also difficult. In addition, dislocation or segregation of germanium (Ge) may occur when forming a SiGe layer with a high temperature treatment and the gate breakdown voltage property suffers.
Thus, the present invention provides a method for forming a MOS transistor with strained-channel, having enhanced strain on the channel region thereof by improving the location and design of stressors therein.